The present invention relates to a wiring structure for a semiconductor integrated circuit device. More particularly, the invention relates to improvements in a multilayer wiring structure for a semiconductor integrated circuit device having a fixed wiring region such as a gate array.
A two layer metal wiring structure is shown as a conventional wiring structure of a semiconductor integrated circuit device of this type in FIGS. 1 and 2. FIG. 1 is a plan view of the two layer metal wiring structure, and FIG. 2 is a sectional view taken along the line II--II of FIG. 1.
In the conventional two layer metal wiring structure shown in FIGS. 1 and 2, reference numeral 1 depicts a semiconductor substrate of a semiconductor integrated circuit, numeral 2 denotes a first insulating layer in the form of silicon oxide or silicon nitride film formed on the semiconductor substrate 1, numeral 3 designates a first metal wiring layer of aluminum formed on the first insulating film layer 2 with a predetermined pattern, numeral 4 indicates a second insulating film layer of silicon oxide or silicon nitride on the first metal wiring layer 3, and numeral 5 illustrates a second metal wiring layer of aluminum formed on the second insulating film layer 4 and connected to the first metal wiring layer 3 via through holes 6 at a predetermined portions thereof.
In the two layer metal wiring structure of this conventional example, the first insulating film layer 2 is first formed on the semiconductor substrate 1, and contact holes are perforated in the first insulating film layer 2 by a photoresist technique generally to form contacts with terminals of circuit elements such as transistors formed in the main surface of the semiconductor substrate 1 (though omitted in the drawings).
Then, after wiring metal is formed on the entire surface of the wafer by bonding, the first metal wiring layer 3 is formed thereon in a predetermined pattern by a photoresist technique. The second insulating film layer 4 for covering them is further formed thereon and through holes 6 are also perforated in the second insulating film layer 4 by a photoresist technique to form contacts with the first metal wiring layer 3. Wiring metal is subsequently formed by bonding to cover the entire surface thereof and the second metal wiring layer 5 is formed by patterning it as predetermined by a photoresist technique. Thereafter, the first and second layer metal wirings 3 and 5 are connected to one another.
Therefore, in the two layer metal wiring structure of each such conventional semiconductor integrated circuit device, at least four photoresist steps must be executed with using four different photomasks in the respective steps. As the result, there arise drawbacks that a development cost of the semiconductor integrated circuit of this type is increased since the photomasks are expensive and wafer processing time is lengthened. These drawbacks cause a small quantity production of various products within short period which is usual in production of semicustomed LSI having common region such as gate arrays to be largely disturbed.